1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for controlling isolation gates, and more particularly during a self-refresh operation of a semiconductor memory device, such having the structure of a shared bit line sense amplifier.
2. Description of the Related Art
A memory cell array of a semiconductor memory device includes one or more banks. Each bank has a plurality of memory blocks, and each memory block includes a plurality of word lines. The memory cells are arranged to form a matrix, one on each of the intersections of a plurality of word lines and a plurality of column lines. Each column line is comprised of a bit line and a complementary bit line.
In general, a volatile semiconductor memory device such as a dynamic random access memory requires a refresh operation at regular intervals in order to prevent the loss of data stored as electric charge.
In a self-refresh mode, the semiconductor memory device selects a word line from a plurality of word lines in each clock period generated by an internal clock oscillator, to perform a refresh operation for refreshing the memory cells connected to the selected word line.
The typical architecture of most semiconductor memory devices such as DRAMs is that the common sense amplifiers are shared between one memory block and an adjacent memory block. When the memory block is selected, a memory cell in the selected memory block should be connected to the common sense amplifier exclusively. Therefore isolation gates are needed between the memory block and common sense amplifiers to prevent unexpected operations in the common sense amplifiers due to an abnormal connection by an unselected memory block. FIG. 1 shows a conventional circuit for controlling an isolation gate of a semiconductor memory device, and related circuits.
Referring to FIG. 1, a semiconductor memory cell array which include four memory blocks 150, 151, 152 and 153 is shown. Each of the memory blocks includes 512 word lines WL0 to W1511. Bit line sense amplifiers 130, 131, 132, 133 and 134 are each shared by the neighboring memory blocks. Isolation gates 140L, 140R, 141L, 141R, 142L, 142R, 143L and 143R are connected respectively between each bit line sense amplifier and the memory blocks corresponding thereto, and perform a switching operation responding to the isolation gate control signals PIS00L, PIS00R, PIS01L, PIS01R, PIS02L, PIS02R, PIS03L and PIS03R, respectively. In the prior art, a control signal directed to isolation gates is only controlled by a block selection signal (BLSi) which is designated to a certain memory block.
Block select signal drivers 120, 121, 122 and 123 buffer block select signals BLK0, BLK1, BLK2 and BLK3, respectively, to generate respective outputs (BLS0, BLS1, BLS2, BLS3). The block select signals BLK0, BLK1, BLK2 and BLK3 are obtained by decoding block information of a row address, and only the block select signal, which refers to a memory block to be accessed, is activated. A refresh operation can be simultaneously performed on the plurality of memory blocks, according to a refresh scheme. At this time, the plurality of block select signals are also simultaneously activated. For example, block information in a semiconductor memory device including four memory blocks, corresponds to 2 bit in row addresses, which are each decoded to generate four block select signals BLK0, BLK1, BLK2 and BLK3. The respective outputs BLS0, BLS1, BLS2 and BLS3 of the block select signal drivers 120, 121, 122 and 123 are applied to isolation gates corresponding to the same memory block and to neighboring isolation gate portions. For example, the output `BLS0` of the block select signal driver 120 is applied to isolation gate control signal generators 110L and 110R, and also to an isolation gate control signal generator 111L. As another example, the output `BLS1` of the block select signal driver 121 is applied to isolation gate control signal generators 111L and 111R, and also to isolation gate control signal generators 110R and 112L. Other outputs are also applied in the above-described manner.
In the structure of the memory cell array of FIG. 1, in the case that memory cells of a memory block 150 are accessed, bit line sense amplifiers 130 and 131 must be activated. At this time, the isolation gates 140L and 140R must be turned on, and the isolation gate 141L must be turned off. In the case that memory cells of the memory block 151 are accessed, the bit line sense amplifiers 131 and 132 must be activated. At this time, the isolation gates 141L and 141R must be turned on, and the isolation gates 140R and 142L must be turned off. That is, the bit line sense amplifiers 130 to 134 are each shared by their neighboring memory blocks, so that the isolation gates connected between the accessed memory block and the neighboring bit line sense amplifiers should be turned on, and the isolation gates connected between a memory block not accessed and the neighboring bit line sense amplifiers should be turned off. Accordingly, the isolation gate control signals PISO0L, PISO0R, PISO1L, PISO1R, PISO2L, PISO2R, PISO3L and PISO3R generated by the isolation gate control signal generators 110L, 110R, 111L, 111R, 112L, 112R, 113L and 113R are activated to a boosted voltage VPP in the case that the corresponding block select signals are activated to a `high` level, and deactivated to a ground voltage VSS in the case that the neighboring block select signals corresponding thereto are activated to a `high` level.
Operation of the self refresh mode is now described in detail with reference to FIG. 2. When a self refresh order is received from an external source, a self refresh set signal PSELF is activated to a `high` level, and then the falling edge of a refresh row active signal PRFH triggers the activation of a self refresh mode signal PSRAS to a `high` level. The refresh low active signal PRFH is generated in a refresh mode, i.e., a self refresh mode or an automatic refresh mode, according to the output POSC of an oscillator, and in a non-refresh mode according to a clock CLK. In the refresh mode, the block select signal is triggered by the refresh row active signal PRFH, to activate to a `high` level. The block select signals BLK0, BLK1, BLK2 and BLK3 are buffered by block select signal drivers 120, 121, 122 and 123, respectively, of FIG. 1, and then output as block driving signals BLS0, BLS1, BLS2 and BLS3, respectively. The block driving signals are applied to an isolation gate control signal generator to turn it on, and to isolation gate control signal generators corresponding to other isolation gates connected to the same bit line sense amplifier, to turn then off. The isolation gate control signals PIS00L, PIS00R, PIS01L, PIS01R, PIS02L, PIS02R, PIS03L and PIS03R are generated according to block driving signals BLS0, BLS1, BLS2 and BLS3. The isolation gate control signals PIS00L, PIS00R, PIS01L, PIS01R, PIS02L, PIS02R, PIS03L and PIS03R each have three possible levels: a power supply voltage VCC when the memory block corresponding thereto, and the neighboring memory blocks, are not accessed; a boosted voltage level VPP when the memory block corresponding thereto is accessed, and a ground voltage VSS when the neighboring memory block is accessed. At this time, the block driving signal is generated only by buffering the block select signal, so that it has a waveform same as that of the refresh row active signal PRFH. That is, the block driving signal has a pulse waveform periodically activated. Accordingly, the level of each of the isolation gate control signals generated by the block driving signals is changed whenever the refresh row active signal PRFH is activated. This continuous change causes bias variations and thus, detrimentally increases power consumption of the memory device.
In a normal mode, one word line is selected from a plurality of word lines and then accessed according to a row address signal applied from an external source. Therefore, the level of each of the isolation gate control signals is changed according to the low active signal. However, in the self-refresh mode, a plurality of word lines are sequentially accessed, so that the level of each of the isolation gate control signals need not be changed whenever the row active signal PRFH is activated but detrimentally are changed.
In detail, in the self-refresh mode, word lines WL0, WL1 and WL2 of a memory block 151 are sequentially accessed. Accordingly, the isolation gate control signals PIS0 need not change during the period from when the word line WL0 of the memory block 151 is accessed, to when the word line WL511 thereof is accessed.
However, in the conventional isolation gate control circuit of FIG. 1, this characteristic of the refresh operation is disregarded. Therefore, as shown in FIG. 2, levels of the isolation gate control signals PIS00L, PIS00R, PIS01L, PIS01R, PIS02L, PIS02R, PIS03L and PIS03R are unnecessarily changed, which causes excessive power consumption.